ADIS16501SLASHPCBZ datasheet(24/45 Pages) AD

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Data Sheet

ADIS16501

THEORY OF OPERATION

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Rev. B | 24 of 45

mode is appropriate for cases where there is averaging (decima-

tion) and/or low-pass filtering of the data.

Figure 44. Burst Read Sequence with BURST_SEL = 0

The sequence of registers (and checksum value) in the burst

read includes the following registers and value: DIAG_STAT,

X_GYRO_LOW, X_GYRO_OUT, Y_GYRO_LOW, Y_GYRO_OUT,

Z_GYRO_LOW, Z_GYRO_OUT, X_ACCL_LOW, X_ACCL_OUT,

Y_ACCL_LOW, Y_ACCL_OUT, Z_ACCL_LOW, Z_ACCL_OUT,

TEMP_OUT, DATA_CNTR, and the checksum value. In these cas-

es, use the following formula to verify the 16-bit checksum value,

treating each byte in the formula as an independent, unsigned, 8-bit

number:

Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +

X_GYRO_LOW, Bits[15:8] + X_GYRO_LOW, Bits[7:0] +

X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +

Y_GYRO_LOW, Bits[15:8] + Y_GYRO_LOW, Bits[7:0] +

Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +

Z_GYRO_LOW, Bits[15:8] + Z_GYRO_LOW, Bits[7:0] +

Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +

X_ACCL_LOW, Bits[15:8] + X_ACCL_LOW, Bits[7:0] +

X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +

Y_ACCL_LOW, Bits[15:8] + Y_ACCL_LOW, Bits[7:0] +

Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +

Z_ACCL_LOW, Bits[15:8] + Z_ACCL_LOW, Bits[7:0] +

Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +

TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +

DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]

32-Bit Burst Mode with BURST_SEL = 1

In 32-bit burst mode with BURST_SEL = 1, a burst contains cali-

brated delta angle and delta velocity data in 32-bit format. This

mode is appropriate for cases where there is averaging (decima-

tion) and/or low-pass filtering of the data.

Figure 45. Burst Read Sequence with BURST_SEL = 1

The sequence of registers (and checksum value) in the burst read

includes the following registers and value: DIAG_STAT, X_DEL-

TANG_LOW, X_DELTANG_OUT, Y_DELTANG_LOW, Y_DEL-

TANG_OUT, Z_DELTANG_LOW, Z_DELTANG_OUT, X_DELT-

VEL_LOW, X_DELTVEL_OUT, Y_DELTVEL_LOW, Y_DELT-

VEL_OUT, Z_DELTVEL_LOW, Z_DELTVEL_OUT, TEMP_OUT,

DATA_CNTR, and the checksum value. In these cases, use the

following formula to verify the 16-bit checksum value, treating each

byte in the formula as an independent, unsigned, 8-bit number:

Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +

X_DELTANG_LOW, Bits[15:8] + X_DELTANG_LOW, Bits[7:0] +

X_DELTANG_OUT, Bits[15:8] + X_DELTANG_OUT, Bits[7:0] +

Y_DELTANG_LOW, Bits[15:8] + Y_DELTANG_LOW, Bits[7:0] +

Y_DELTANG_OUT, Bits[15:8] + Y_DELTANG_OUT, Bits[7:0] +

Z_DELTANG_LOW, Bits[15:8] + Z_DELTANG_LOW, Bits[7:0] +

Z_DELTANG_OUT, Bits[15:8] + Z_DELTANG_OUT, Bits[7:0] +

X_DELTVEL_LOW, Bits[15:8] + X_DELTVEL_LOW, Bits[7:0] +

X_DELTVEL_OUT, Bits[15:8] + X_DELTVEL_OUT, Bits[7:0] +

Y_DELTVEL_LOW, Bits[15:8] + Y_DELTVEL_LOW, Bits[7:0] +

Y_DELTVEL_OUT, Bits[15:8] + Y_DELTVEL_OUT, Bits[7:0] +

Z_DELTVEL_LOW, Bits[15:8] + Z_DELTVEL_LOW, Bits[7:0] +

Z_DELTVEL_OUT, Bits[15:8] + Z_DELTVEL_OUT, Bits[7:0] +

TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] + DATA_CNTR,

Bits[15:8] + DATA_CNTR, Bits[7:0]

LATENCY

Table 8 contains the group delay for each inertial sensor when

the ADIS16501 is operating with the factory default settings for

the FILT_CTRL (see Table 102) and DEC_RATE (see Table 110)

registers.

Table 8. Group Delay with No Filtering, Wide Bandwidth Option, MSC_CTRL,

Bit 4 = 0

Inertial Sensor

Group Delay (ms)1

Accelerometer

1.37

Gyroscope (X-Axis)

1.56

Gyroscope (Y-Axis)

1.56

Gyroscope (Z-Axis)

1.34

1 In this context, latency represents the time between the motion (linear acceler-

ation and/or angular rate of rotation) and the time that the representative data

is available in the output data register.

Table 9. Group Delay with No Filtering, 370 Hz Bandwidth, MSC_CTRL, Bit 4 =

Inertial Sensor

Group Delay (ms)1

Accelerometer

2.00

Gyroscope (X-Axis)

1.80

Gyroscope (Y-Axis)

1.80

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