Z8F2480 datasheet(97/412 Pages) ZILOG

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PS025017-1222

P R E L I M I N A R Y

Interrupt Controller

Z8 Encore! XP® F1680 Series

Product Specification

Example 1.

A poor coding style that can result in lost interrupt requests:

LDX r0, IRQ0

AND r0, MASK

LDX IRQ0, r0

To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt

Request 0 Register:

Example 2.

A good coding style that avoids lost interrupt requests:

ANDX IRQ0, MASK

8.3.4. Software Interrupt Assertion

Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt

Request Register triggers an interrupt (assuming that the interrupt is enabled). When the

interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request

Zilog recommends not using a coding style to generate software interrupts by setting bits

in the Interrupt Request registers. All incoming interrupts received between execution of

the first LDX command and the final LDX command are lost. See Example 3, which fol-

lows.

Example 3.

A poor coding style that can result in lost interrupt requests:

LDX r0, IRQ0

OR r0, MASK

LDX IRQ0, r0

To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt

Request registers:

Example 4.

A good coding style that avoids lost interrupt requests:

ORX IRQ0, MASK

8.4.

Interrupt Control Register Definitions

For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail

Trap and the Watchdog Oscillator Fail Trap, the Interrupt Control registers enable

individual interrupts, set interrupt priorities and indicate interrupt requests.

Caution:

Z8F2480 Datasheet(PDF) 97 Page - Zilog, Inc.