LTC2489CDEPBF datasheet(11/24 Pages) LINER

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LTC2489

2489f

The Start and Stop Conditions

A Start (S) condition is generated by transitioning SDA from

high to low while SCL is high. The bus is considered to be

busy after the Start condition. When the data transfer is

ﬁnished, a Stop (P) condition is generated by transitioning

SDA from low to high while SCL is high. The bus is free

after a Stop is generated. Start and Stop conditions are

always generated by the master.

When the bus is in use, it stays busy if a Repeated Start

(Sr) is generated instead of a Stop condition. The repeated

Start timing is functionally identical to the Start and is

used for writing and reading from the device before the

initiation of a new conversion.

Data Transferring

After the Start condition, the I2C bus is busy and data

transfer can begin between the master and the addressed

slave. Data is transferred over the bus in groups of nine

bits, one byte followed by one acknowledge (ACK) bit. The

master releases the SDA line during the ninth SCL clock

cycle. The slave device can issue an ACK by pulling SDA

low or issue a Not Acknowledge (NAK) by leaving the SDA

line high impedance (the external pull-up resistor will hold

the line high). Change of data only occurs while the clock

line (SCL) is low.

DATA FORMAT

After a Start condition, the master sends a 7-bit address

followed by a read/write (R/W) bit. The R/W bit is 1 for

a read request and 0 for a write request. If the 7-bit ad-

dress matches the hard wired, LTC2489’s address (one of

9 pin-selectable addresses) the device is selected. When

the device is addressed during the conversion state, it will

not acknowledge R/W requests and will issue a NAK by

leaving the SDA line high. If the conversion is complete,

the LTC2489 issues an ACK by pulling the SDA line low.

The LTC2489 has two registers. The output register (24

bits long) contains the last conversion result. The input

DATA OUTPUT FORMAT

The output register contains the last conversion result.

After each conversion is completed, the device automati-

cally enters the sleep state where the supply current is

reduced to 1μA. When the LTC2489 is addressed for a read

operation, it acknowledges (by pulling SDA low) and acts

as a transmitter. The master/receiver can read up to three

bytes from the LTC2489. After a complete read operation

(3 bytes), a new conversion is initiated. The device will

NAK subsequent read operations while a conversion is

being performed.

The data output stream is 24 bits long and is shifted out

on the falling edges of SCL (see Figure 3a). The ﬁrst bit

is the conversion result sign bit (SIG) (see Tables 1 and

2). This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN

corresponds to the selected input signal IN+ – IN–). The

second bit is the most signiﬁcant bit (MSB) of the result.

The ﬁrst two bits (SIG and MSB) can be used to indicate

over and under range conditions (see Table 2). If both bits

are HIGH, the differential input voltage is equal to or above

+FS. If both bits are set low, the input voltage is below

–FS. The function of these bits is summarized in Table

2. The 16 bits following the MSB bit are the conversion

SDA

SCL

SSr

tHD(SDA)

tHD(DAT)

tSU(STA)

tSU(STO)

tSU(DAT)

tLOW

tHD(SDA)

tSP

tBUF

tHIGH

2489 F02

Figure 2. Deﬁnition of Timing for Fast/Standard Mode Devices on the I2C Bus

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