LTC3214

9

3214fa

compare the amount of achievable capacitance for a given

case size rather than comparing the specified capacitance

value. For example, over rated voltage and temperature

conditions, a 1

µF,10V,Y5Vceramiccapacitorina0603case

may not provide any more capacitance than a 0.22

µF, 10V,

X7R available in the same case. The capacitor

manufacturer’s data sheet should be consulted to determine

what value of capacitor is needed to ensure minimum

capacitances at all temperatures and voltages.

Table 1 shows a list of ceramic capacitor manufacturers

and how to contact them.

Table 1. Recommended Capacitor Vendors

AVX

www.avxcorp.com

Kemet

www.kemet.com

Murata

www.murata.com

Taiyo Yuden

www.t-yuden.com

Vishay

www.vishay.com

TDK

www.tdk.com

Layout Considerations and Noise

Due to the high switching frequency and the transient

currents produced by the LTC3214, careful board layout is

necessary. A true ground plane and short connections to

all capacitors will improve performance and ensure proper

regulation under all conditions. An example of such a

layout is shown in Figure 4.

very high edge rate waveforms. The large dv/dt on these

pins can couple energy capacitively to adjacent PCB runs.

Magnetic fields can also be generated if the flying capaci-

tors are not close to the LTC3214 (i.e., the loop area is

large). To decouple capacitive energy transfer, a Faraday

shield may be used. This is a grounded PCB trace between

the sensitive node and the LTC3214 pins. For a high quality

AC ground, it should be returned to a solid ground plane

that extends all the way to the LTC3214.

The following guidelines should be followed when design-

ing a PCB layout for the LTC3214.

• The Exposed Pad should be soldered to a large copper

plane that is connected to a solid, low impedance

ground plane using plated, through-hole vias for proper

heat sinking and noise protection.

be placed as close to the part as possible.

• The flying capacitors must also be placed as close to the

part as possible. The traces running from the pins to the

capacitor pads should be as wide as possible.

possible. This is necessary to minimize inductance,

as well as provide sufficient area for high current

applications.

• LED pads must be large and should be connected to as

much solid metal as possible to ensure proper heat

sinking.

APPLICATIO S I FOR ATIO

PIN 1

C1

C2

3214 F04

Figure 4. Example Board Layout