12.0 Switching Characteristics (25°C)

The switching characteristics (25°C) for the I/O clocks are shown in the diagram of Figure 5. Each switch timing characteristic for each

waveform is represented by its symbolic acronym. Each corresponding switching time is defined in the Table 12-A. Note: Only one

video output is shown because all four videos have identical electrical characteristics. The only physical difference is in Section 4,

output, VOUT4. Section 4 has only 6 sensor chips, hence its active scan is shorter by 64 pixels.

Figure 5: Module Timing Diagram

Table 12-A: Timing Symbol’s Definition and Timing Values

Item

Symbol

Min.

Typ.

Max.

Units

Clock cycle time

to

0.20

4.0

µs

Clock pulse width

tw

50

ns

Clock duty cycle

25

75

%

Prohibit crossing time of SP

(1)

tprh

0

ns

Data setup time

tds

20

ns

Data hold time

tdh

0

ns

Signal delay time

tdl

20

ns

Signal settling time

tsh

100

ns

Note:

1.

"Prohibit crossing of start pulse" is to indicate that the SP should not be active high between any two consecutive clock pulses, specifically, between two

consecutive low-going clock pulses. See the timing diagram. All falling clock edges under an active high SP loads the internal shift register, therefore the SP must

be active over only one falling clock edge. High SP over all rising clock edge is ignored by the shift register. One simple way to ensure that the SP will not be

actively high during two consecutive falling clock edges is to generate the SP on a rising clock edge and terminate it on the following rising clock edge.

12

AMI Semiconductor – May 06, M-20548-001

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