AMIS-710600-A8: 600dpi CIS Module

Data Sheet

5.0 Timing Characteristics of the Module (25°C)

The input control clocks and video pixel output relationships are depicted in Figure 3. As indicated, the internal shift register is loaded

on the falling edges of the module's clock, CP and during this time the SP is high or true. To ensure that only one shift register pulse is

loaded into the shift register during any one line scan, only one SP is allowed to go high for one CP cycle going low. After loading the

shift register, the SP is to remain low throughout the remainder of the line scan; otherwise multiple start pulses will load into the shift

register. To prevent this phenomenon, as the timing diagram shows, SP should occur only once in one CP cycle. When only one pulse

is loaded in the register, a single pulse shifts down the register, accessing a single photo-site with each shift and sequentially reading it

out onto the common video line where the video pixel is amplified and produced at the output I/O.

Figure 3: Timing Diagram of SP Relative to First Pixel

The call outs for the switching characteristics in Figure 3 are given in Table 6. This table defines the symbols used in the timing diagram

and calls out their time durations.

Table 6: Timing Definition and Specifications

Item

Symbol

Min.

Typ.

Max.

Units

Clock cycle time

to

290

7440

ns

Clock pulse width

tw

71

ns

Clock duty cycle

25

75

%

Prohibit crossing time of SP

tprh

30

ns

Data setup time

tds

30

ns

Data hold time

tdh

30

ns

Signal delay time

tdl

50

ns

Signal sample and hold time

tsh

120

ns

5

AMI Semiconductor – July. 06, M-20597-001

www.amis.com