Absolute Maximum Ratings:

Parameters

Symbol

Maximum Rating

Units

Power Supply Voltage

VDD

10

Volts

Power Supply Current

IDD

<2.0

ma

Input clock pulse (high level)

Vih

Vdd + 0.5

Volts

Input clock pulse (low level)

Vil

-0.25

Volts

Operating Temperature

Top

0 to 50

Operating Humidity

Hop

10 to 85

RH %

Storage Temperature

Tstg

-25 to 75

Storage Humidity

Hstg

10 to 90

RH %

Recommended Operating Conditions at Room Temperature

Parameters

Symbol

Min.

Typical

Max.

Units

Notes

Power Supply

VDD

4.5

5.0

5.5

Volts

Input clock pulses high level

Vih

2.8

5.0

VDD

Volts

1

Input clock pulse low level

Vil

0

0

0.8

Volts

1

Operating high level exposed output

Iout

2

Clock Frequency

f

0.1

2.0

5.0

MHz

3

Clock pulse duty cycle

25

%

4

Clock pulse high durations

tw

0.125

µsec

4

Integration time

Tint

1.3

10

ms

3

Operating Temperature

Top

25

50

Notes:

(1) Applies to both CP and SP.

(2) The output is a current that is proportional to the charges, which are integrated on the

phototransistor’s base via photon-to-electron conversion. Accordingly during read out, these

charges are discharged from the base through the transistor’s emitter proportionally to the Beta

of the phototransistor. Hence, the emitter current, that flows to the output video line, is the

signal that is proportional to the photon integrated charges. To gain the optimum performance,

the signal interfacing circuits are designed consistently with this signal process. The video

signal current is made to flow into a virtual ground, while the signal extraction circuit is made to

integrate these charges that converts these charges into the output signal voltage. The circuit

used for the converting the current charge to voltage is attached to this document as a

separate sheet.

(3) Although the clock frequency will operate the device at less than 100KHz, it is

recommended that the device be operated above 500KHz to maintain the devices performance

characteristic.

(4) The clock duty cycle typically is 25 %. However, it can operate with duty cycle as large as

50 %. This specified duty cycle is suggested because the 25 % of clock time, or the positive

time of the clock, is used in the reset process, while the remainder of the time is used inextracting

the signal during each pixel. Accordingly at low clock frequencies, it would help the

PAGE 4 OF 7 PI3012A, 6/9/99