EOS fall delay

tefdl

70

ns

tdl

100

ns

tsh

200

ns

Table 5. Timing Symbols and Definition

Notes:

1. Clock pulse width varies with frequency, as it was explained foregoing paragraphs.

2. Prohibit crossing time to insure that two start pulses are not locked into the shift register

during any single scan time.

3. Pixel delay times and settling time depend on the output amplifier. The numbers, which are

given, are measured with an EL2044 amplifier. The faster the amplifier, the faster the signal

will respond. In other words, faster rise and settle times are faster.

Output Circuits for Video Signal

The circuit in following page shows the PI3034A in a CIS module application. It also serves not only a

reference for the above operational explanation given in note 3 under Table 2. Electro-Optical

Characteristics; it further exemplifies a method for interfacing the device in developing a 1728 element,

A4 size CIS module.

Item

Symbol

Minimum

Mean

Maximum

Units

Clock cycle time

to

1000

10000

ns

tw

250

ns

Clock duty cycle

25

50

75

%

Data setup time

tds

50

ns

Data hold time

tdh

20

ns

tprh

30

ns

EOS rise delay

terdl

60

ns

Page 5 of 7 - PI3034A, 06/15/03