AD3552R datasheet(60/70 Pages) AD

60 / 70 page

Data Sheet

AD3552R

REGISTERS

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Rev. B | 60 of 70

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Hardware LDAC Mask Register, Fast Mode

Address: 0x28, Reset: 0x00, Name: HW_LDAC_16B

This register controls the masking of the external LDAC signal to latch data into each of the DAC channels.

Table 45. Bit Descriptions for HW_LDAC_16B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

HW_LDAC_MASK_CH1

Hardware LDAC Mask for Channel 1. This bit controls the latching of data

into the DAC register when the LDAC signal is asserted.

0x0

R/W

0 Data is latched in DAC Register 1 when the LDAC pin is asserted.

1 LDAC signal masked for Channel 1. DAC register is not updated when

LDAC is asserted.

HW_LDAC_MASK_CH0

Hardware LDAC Mask for Channel 0. This bit controls the latching of data

into the DAC register when the LDAC signal is asserted.

0x0

R/W

0 Data is latched in DAC Register 0 when the LDAC pin is asserted.

1 LDAC signal masked for Channel 0. DAC register is not updated when

LDAC is asserted.

DAC Register for Channel 0, Fast Mode

Address: 0x29, Reset: 0x0000, Name: CH0_DAC_16B

This register contains the data currently played on DAC Channel 0.

Table 46. Bit Descriptions for CH0_DAC_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

DAC_DATA0

Channel 0 DAC Data.

0x0

R/W

DAC Register for Channel 1, Fast Mode

Address: 0x2B, Reset: 0x0000, Name: CH1_DAC_16B

This register contains the data currently played on DAC Channel 1.

AD3552R Datasheet(PDF) 60 Page - Analog Devices

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