AD8065 datasheet(39/70 Pages) AD

39 / 70 page

Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. B | 39 of 70

Table 16. Alarm Mask Register and Corresponding Error Source

Bit Number

Alarm Mask Register Bit Name

Error Source Register Name

Error Source Bit Name

REF_RANGE_ALARM_MASK

ERR_STATUS

REF_RANGE_ERR_STATUS

CLOCK_COUNT_ALARM_MASK

INTERFACE_STATUS_A

CLOCK_COUNTING_ERROR

MEM_CRC_ALARM_MASK

ERR_STATUS

MEM_CRC_ERR_STATUS

SPI_CRC_ERR_ALARM_MASK

INTERFACE_STATUS_A

INVALID_OR_NO_CRC

WRITE_TO_READ_ONLY_ALARM_MASK

INTERFACE_STATUS_A

WRITE_TO_READ_ONLY_REGISTER

PARTIAL_REGISTER_ACCESS_ALARM_MASK

INTERFACE_STATUS_A

PARTIAL_REGISTER_ACCESS

REGISTER_ADDRESS_INVALID_ALARM_MASK INTERFACE_STATUS_A

REGISTER_ADDRESS_INVALID

ERR_STATUS Register

VREF Detection

The REF_RANGE_ERR_STATUS bit in the ERR_STATUS register

is set when the reference voltage drops below 1 V for more than

5 ms. The error is detected irrespective of the reference voltage

source, whether it is generated internally or provided externally via

the VREF pin. This feature is useful to detect an interruption in the

external reference voltage or an overload condition on the VREF pin

when the internal reference is shared with another device.

SPI Mode Error

The SPI mode error is produced during streaming when the ad-

dress pointer crosses the boundary between the secondary and

the primary region with the SPI interface configured in synchro-

nous dual SPI mode or dual SPI mode because this region can

only be accessed in quad SPI mode or classic SPI mode. The

DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS bit is set in

the ERR_STATUS register.

The AD3552R includes an internal CRC for the register map and

the read only memory (ROM). The CRC is executed every 4.1 μs,

and only includes the primary region of the register map because

the secondary region is expected to be continuously written. The

CRC can be disabled by clearing the MEM_CRC_EN bit in the

INTERFACE_CONFIG_D register. If a CRC error is detected, the

MEM_CRC_ERR_STATUS bit is set in the ERR_STATUS register.

It is advisable to reset the device if this error occurs.

Reset Status

The RESET_ STATUS bit in the ERR_STATUS register indicates

that the AD3552R has been reset, either internally (POR or SW

reset) or externally (via the RESET pin). The RESET_STATUS bit

is set when the POR completes correctly. It is useful to detect

unexpected reset conditions, such as a dip in power supply, and

take corrective actions.

The RESET_STATUS bit causes the assertion of the ALERT pin

and it is not maskable. Therefore, it must be cleared after reset or

power-up to be able to detect new events via the ALERT signal.

INTERFACE_STATUS_A Register

Device Busy

The INTERFACE_NOT_READY bit in the INTERFACE_STATUS_A

know when the device is ready to receive data from the controller.

SPI Clock Counter

The error reported in the CLOCK_COUNTING_ERR bit is produced

when the number of SCLK cycles is not in accordance with the

amount required to shift a multiple of 8 bits, taking into account

the SPI mode (quad, dual, or single) and the DDR mode. The

CLOCK_COUNTING_ERR bit is set in the ERR_STATUS register.

Valid combinations are shown in Table 17.

Table 17. Clock Cycles Required to Transfer One Byte

SPI Mode

DDR

Clock Cycles for 1 Byte

Single SPI

Yes

Dual SPI

Yes

Quad SPI

Yes

SPI CRC

The INVALID_OR_NO_CRC bit in the INTERFACE_STATUS_A

the SPI transaction is missing or it does not match the calculated

value. To clear this error, write 1 to this bit. Note that because CRC

is enabled, this SPI transaction must have a valid CRC code to

succeed.

Write to Read Only Register

If the host tries to write to a read only register, the

WRITE_TO_READ_ONLY_REGISTER bit field is asserted in the

INTERFACE_STATUS_A register. To clear this error, write 1 to the

WRITE_TO_READ_ONLY_REGISTER bit.

AD8065 Datasheet(PDF) 39 Page - Analog Devices

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