AD8065 datasheet(40/70 Pages) AD

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Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. B | 40 of 70

Partial Register Access

The PARTIAL_REGISTER_ ACCESS bit in the INTERFACE_STA-

TUS_A register is set when a multibyte register is accessed for read

or write partially, which means that the transaction ends before all

the bytes of a multibyte register have been accessed. To clear this

error, write 1 to the PARTIAL_REGISTER_ ACCESS bit.

Invalid Access

When the host tries to access an invalid register address, the REG-

ISTER_ADDRESS_INVALID bit is set in the INTERFACE_STA-

TUS_A register. To clear this error, write 1 to this bit.

ALERT PIN

When one of the errors listed in Table 16 is detected and its

corresponding bit in the ERR_ALARM_MASK register is set to 0,

the ALERT pin is asserted. This pin can be used as an interrupt line

for the CPU to take action when an error condition arises.

In addition, the ALERT pin is asserted when the RESET_STATUS

bit is asserted in the ERR_STATUS register. This condition is not

maskable. Therefore, the RESET_STATUS bit must be cleared

after initialization to use the ALERT pin. If the pin remains asserted

after clearing all the error sources, it means that there has been

an error during the initialization of the device and it must be power

cycled.

The ALERT pin requires a pull-up resistor that can be provided

externally or internally. The chip incorporates an internal 2.5 kΩ

pull-up resistor that can be enabled by setting the ALERT_ENA-

BLE_PULLUP bit in the INTERFACE_CONFIG_D register.

The ALERT pin is deasserted when all the errors are cleared in

their corresponding registers.

DEVICE ID

The AD3552R includes numerous registers providing silicon related

information. The following registers can be used to identify that the

correct chip type and version are assembled:

►

CHIP_TYPE

►

PRODUCT_ID_L

►

PRODUCT_ID_H

►

CHIP_GRADE

►

SPI_REVISION

►

VENDOR_L

►

VENDOR_H

SUMMARY OF INTERFACE ACCESS MODES

Finding the correct SPI mode can be difficult given the number of

modes and the restrictions on specific registers or memory regions,

specially when not using QSPI. To facilitate the implementation

of the driver in the CPU, a decision tree is presented in Figure

92. Figure 92 depicts how the driver must proceed depending on

the configuration of the interface and the registers being accessed

when the QSPI pin is low. The decision tree is much simpler when

QSPI is high, as shown in Figure 93.

Figure 92. Register Access Modes when QSPI Pin is Low

AD8065 Datasheet(PDF) 40 Page - Analog Devices

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