AD8065 datasheet(29/70 Pages) AD

29 / 70 page

Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. B | 29 of 70

Multibyte registers can be read in a single SPI transaction or each

byte can be addressed separately. If an SPI read transaction to

a multibyte register is attempted on a per byte basis, the PARTI-

AL_REGISTER_ACCESS bit in the INTERFACE_ STATUS_A reg-

ister is set. For example, the VENDOR_ID register is 2 bytes long,

and the addresses of its least significant byte and most significant

byte are 0x0C and 0x0D, respectively. Figure 72 and Figure 73

show write and read transactions to a multibyte register (2 bytes)

for address ascending and descending mode, respectively. See the

Address Direction section for more information on selecting address

descending (auto-decrementing) or ascending (auto-incrementing).

Address Direction

The address direction option is used to control whether the register

address is set to automatically increment (address ascending) or

decrement (address descending) when transferring multiple bytes

of data in a single data phase (for example, when accessing

multibyte registers, as shown in Figure 72 and Figure 73, or when

accessing multiple registers with streaming mode, as shown in

Figure 75).

Address direction is selected with the ADDR_DIRECTION bit in

the INTERFACE_CONFIG_A register. If ADDR_DIRECTION is set

to 0, the address decrements after each byte is accessed. If

ADDR_DIRECTION is set to 1, the address increments after each

byte is accessed.

When accessing multibyte registers, use descending addresses to

shift in the most significant byte first.

Multibyte registers from Address 0x29 onwards can only be ac-

cessed in descending mode.

Single Instruction Mode

When the SINGLE_INSTRUCTION bit in the INTERFACE_CON-

FIG_B register is set to 1, streaming mode is disabled, and single

instruction mode is enabled. In single instruction mode, the data

phase only contains data for a single register, and each data phase

must be followed by a new instruction phase, even if CS remains

low. Single instruction mode allows the digital host to quickly read

from and write to registers with nonadjacent addresses in a single

SPI frame, whereas streaming mode only allows either reading or

writing to contiguous registers without pulsing CS high to initiate a

new instruction phase.

Figure 74 shows an example of an SPI transaction in single instruc-

tion mode with the following register accesses:

►

Sets the output range.

►

Enables the output stage.

►

Reads the CHIP_TYPE register.

Figure 74. Single Instruction Mode Register Access Example with Address Descending

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