AD8065 datasheet(2/70 Pages) AD

2 / 70 page

Data Sheet

AD3552R

TABLE OF CONTENTS

analog.com

Rev. B | 2 of 70

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................1

Specifications........................................................ 4

Electrical Characteristics.................................... 4

AC Characteristics..............................................5

Timing Characteristics........................................6

Absolute Maximum Ratings................................. 11

Thermal Resistance..........................................11

ESD Caution.....................................................11

Pin Configuration and Function Descriptions...... 12

Typical Performance Characteristics................... 14

Terminology......................................................... 24

Theory of Operation.............................................26

Product Description.......................................... 26

DAC Architecture..............................................26

Predefined Output Voltage Spans....................26

Custom Output Voltage Span...........................27

Transfer Function............................................. 27

VREF..................................................................27

SPI Register Map Access.................................27

Serial Interface................................................. 34

DAC Update Modes......................................... 37

Power-Down.....................................................38

Reset................................................................38

Error Detection................................................. 38

Alert Pin............................................................40

Device ID..........................................................40

Summary of Interface Access Modes...............40

Registers............................................................. 42

Interface Register Details................................. 45

DAC Register Details....................................... 54

Applications Information...................................... 68

Power Supply Recommendations.................... 68

Combining DAC Channels............................... 68

Layout Guidelines.............................................68

Outline Dimensions............................................. 70

Ordering Guide.................................................70

Evaluation Boards............................................ 70

REVISION HISTORY

2/2023—Rev. A to Rev. B

Changed 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC to Dual Channel, 16-Bit, 33 MUPS, Multispan,

Multi-IO SPI DAC........................................................................................................................................... 1

Changed DVDD to DVDD, IOVDD to VLOGIC, VREF to VREF, AVDD to AVDD, VDD to AVDDD (Throughout)... 1

Changes to Features Section.......................................................................................................................... 1

Changes to General Description Section and Table 1..................................................................................... 1

Changes to Figure 1 ....................................................................................................................................... 1

Changes to Table 2..........................................................................................................................................4

Changes to Table 3..........................................................................................................................................5

Change to Table 5.......................................................................................................................................... 11

Changes to Figure 13 and Table 7.................................................................................................................12

Change to Figure 32 ..................................................................................................................................... 17

Changes to Figure 60 and Figure 61............................................................................................................. 21

Changes to Figure 62, and Figure 64 to Figure 66........................................................................................ 22

Added Figure 67; Renumbered Sequentially................................................................................................. 22

Added Figure 68............................................................................................................................................ 23

Changes to Relative Accuracy or Integral Nonlinearity (INL) Section ...........................................................24

Changes to Differential Nonlinearity (DNL) Section ......................................................................................24

Changes to DC PSRR and AC PSRR Section ............................................................................................. 24

Changes to Output Voltage Settling Time Section ........................................................................................24

Changes to Digital-to-Analog Glitch Impulse Section ................................................................................... 24

Changes to Digital Feedthrough Section ...................................................................................................... 24

Changes to Output Noise Spectral Density Section ..................................................................................... 24

Changes to Total Harmonic Distortion (THD) Section ...................................................................................24

Changes to DC Crosstalk Section................................................................................................................. 25

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