Data Sheet

AD5122/AD5142

SPECIFICATIONS

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Rev. D | 8 of 27

INTERFACE TIMING SPECIFICATIONS

VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4. SPI Interface1

Parameter2

Test Conditions/Comments

Min

Typ

Max

Unit

Description

t1

VLOGIC > 1.8 V

20

ns

SCLK cycle time

VLOGIC = 1.8 V

30

ns

t2

VLOGIC > 1.8 V

10

ns

SCLK high time

VLOGIC = 1.8 V

15

ns

t3

VLOGIC > 1.8 V

10

ns

SCLK low time

VLOGIC = 1.8 V

15

ns

t4

10

ns

SYNC to SCLK falling edge setup time

t5

5

ns

Data setup time

t6

5

ns

Data hold time

t7

10

ns

SYNC rising edge to next SCLK fall ignored

t83

20

ns

Minimum SYNC high time

t94

50

ns

SCLK rising edge to SDO valid

t10

500

ns

SYNC rising edge to SDO pin disable

1 Refer to the AN-1248 for additional information about the serial peripheral interface.

2 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3 Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 5).

4 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.

Table 5. Control Pins

Parameter

Min

Typ

Max

Unit

Description

t1

0.1

10

µs

RESET low time

tEEPROM_PROGRAM1

15

50

ms

Memory program time (not shown in Figure 5)

tEEPROM_READBACK

7

30

µs

Memory readback time (not shown in Figure 5)

tPOWER_UP2

75

µs

Start-up time (not shown in Figure 5)

tRESET

30

µs

Reset EEPROM restore time (not shown in Figure 5)

1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.

2 Maximum time after VDD − VSS is equal to 2.3 V.

SHIFT REGISTER AND TIMING DIAGRAMS

Figure 2. Input Shift Register Contents