Data Sheet

AD5122/AD5142

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. D | 11 of 27

Figure 6. 16-Lead LFCSP Pin Configuration

Table 8. 16-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Ground Pin, Logic Ground Reference.

2

A1

Terminal A of RDAC1. VSS ≤ VA ≤ VDD.

3

W1

Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.

4

B1

Terminal B of RDAC1. VSS ≤ VB ≤ VDD.

5

VSS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

6

A2

Terminal A of RDAC2. VSS ≤ VA ≤ VDD.

7

W2

Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.

8

B2

Terminal B of RDAC2. VSS ≤ VB ≤ VDD.

9

VDD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

10

VLOGIC

Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

11

SCLK

Serial Clock Line. Data is clocked in at the logic low transition.

12

SDI

Serial Data Input.

13

SDO

Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.

14

SYNC

Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.

15

INDEP

Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated memory location. If INDEP is

enabled, it cannot be disabled by software.

16

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to

VLOGIC.

EPAD

Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is

recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.

Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration

Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions

Pin No.

Mnemonic

Description

1

INDEP

Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated memory location. If INDEP is

enabled, it cannot be disabled by software.

2

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to

VLOGIC.

3

GND

Ground Pin, Logic Ground Reference.