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Data Sheet

AD5122/AD5142

THEORY OF OPERATION

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The AD5122/AD5142 digital programmable potentiometers are de-

signed to operate as true variable resistors for analog signals within

the terminal voltage range of VSS < VTERM < VDD. The resistor wiper

position is determined by the RDAC register contents. The RDAC

of resistance settings. A secondary register (the input register) can

preload the RDAC register data.

The RDAC register can be programmed with any position setting

using the SPI interface (depending on the model). When a desira-

ble wiper position is found, this value can be stored in the EEPROM

memory. Thereafter, the wiper position is always restored to that

position for subsequent power-ups. The storing of EEPROM data

takes approximately 15 ms; during this time, the device is locked

and does not acknowledge any new command, preventing any

changes from taking place.

RDAC REGISTER AND EEPROM

The RDAC register directly controls the position of the digital poten-

tiometer wiper. For example, when the RDAC register is loaded with

0x80 (AD5142, 256 taps), the wiper is connected to half scale of

the variable resistor. The RDAC register is a standard logic register;

there is no restriction on the number of changes allowed.

It is possible to both write to and read from the RDAC register using

the digital interface (see Table 10).

The contents of the RDAC register can be stored to the EEPROM

using Command 9 (see Table 16). Thereafter, the RDAC register

always sets at that position for any future on-off-on power supply

sequence. It is possible to read back data saved into the EEPROM

with Command 3 (see Table 10).

Alternatively, the EEPROM can be written to independently using

Command 11 (see Table 16).

INPUT SHIFT REGISTER

For the AD5122/AD5142, the input shift register is 16 bits wide, as

shown in Figure 2. The 16-bit word consists of four control bits,

followed by four address bits and by eight data bits.

If the AD5122 RDAC or EEPROM registers are read from or written

to, the lowest data bit (Bit 0) is ignored.

Data is loaded MSB first (Bit 15). The four control bits determine the

function of the software command as listed in Table 10 and Table

16.

SPI SERIAL DATA INTERFACE

The AD5122/AD5142 contain a 4-wire, SPI-compatible digital inter-

face (SDI, SYNC, SDO, and SCLK). The write sequence begins by

bringing the SYNC line low. The SYNC pin must be held low until

the complete data-word is loaded from the SDI pin. Data is loaded

in at the SCLK falling edge transition, as shown in Figure 3 and

Figure 4. When SYNC returns high, the serial data-word is decoded

according to the instructions in Table 16.

To minimize power consumption in the digital input buffers when

the device is enabled, operate all serial interface pins close to the

VLOGIC supply rails.

SYNC Interruption

In a standalone write sequence for the AD5122/AD5142, the SYNC

line is kept low for 16 falling edges of SCLK, and the instruction

is decoded when SYNC is pulled high. However, if the SYNC line

is kept low for less than 16 falling edges of SCLK, the input shift

invalid.

SDO Pin

The serial data output pin (SDO) serves two purposes: to read back

the contents of the control, EEPROM, RDAC, and input registers

using Command 3 (see Table 10 and Table 16), and to connect the

AD5122/AD5142 to daisy-chain mode.

The SDO pin contains an internal open-drain output that needs an

external pull-up resistor. The SDO pin is enabled when SYNC is

pulled low, and the data is clocked out of SDO on the rising edge of

SCLK, as shown in Figure 3 and Figure 4.

Daisy-Chain Connection

Daisy chaining minimizes the number of port pins required from the

controlling IC. As shown in Figure 40, the SDO pin of one package

must be tied to the SDI pin of the next package. The clock period

can be increased because of the propagation delay of the line

between subsequent devices. When two AD5122/AD5142 devices

are daisy chained, 32 bits of data are required. The first 16 bits

assigned to U2, and the second 16 bits assigned to U1, as shown

in Figure 41. Keep the SYNC pin low until all 32 bits are clocked

into their respective serial registers. The SYNC pin is then pulled

high to complete the operation. A typical connection is shown in

Figure 40.

To prevent data from mislocking (for example, due to noise) the

device includes an internal counter, if the clock falling edges count

is not a multiple of 8, the device ignores the command. A valid clock

count is 16, 24, or 32. The counter resets when SYNC returns high.

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