TDA4841 datasheet(34/60 Pages) PHILIPS

34 / 60 page

1999 Oct 25

Philips Semiconductors

Product speciﬁcation

I2C-bus autosync deﬂection controller for

PC monitors

TDA4841PS

I2C-BUS PROTOCOL

Data format

The format of data for the I2C-bus is given in Table 4.

Table 4

Data format

Notes

1. S = START condition.

2. SLAVE ADDRESS (MAD) = 1000 1100.

3. A = acknowledge, generated by the slave. No acknowledge is given, if the supply voltage is below 8.2 V for start-up

and 8.0 V for shut-down procedure.

4. SUBADDRESS (SAD).

5. DATA byte. If more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is

performed.

6. P = STOP condition.

S(1)

SLAVE ADDRESS(2)

A(3)

SUBADDRESS(4)

A(3)

DATA(5)

A(3)

P(6)

It should be noted that clock pulses according to the

400 kHz specification are accepted for 3.3 V and 5 V

applications (reference level = 1.8 V).

Default register values after power-up are random.

All registers have to be preset via software before the soft

start is enabled.

It should be noted that if register contents are changed

during the vertical scan, this might result in a visible

interference on the screen. The cause for this interference

is the abrupt change of picture geometry which takes effect

at random locations within the visible picture. To avoid this

kind of interference, at least the adjustment of some critical

geometry parameters should be synchronized with the

vertical flyback. The TDA4841PS offers a feature to

synchronize any I2C-bus adjustment with the internal

vertical flyback pulse. For this purpose the IC offers two

different modes for the handling of I2C-bus data:

• Direct mode

• Buffered mode.

Direct mode

The direct mode is selected by setting the MSB of the

I2C-bus register subaddress to logic 0.

Any I2C-bus command is executed immediately after it

was received, so the adjustment takes effect immediately

after the end of I2C-bus transmission.

This mode should be used if many register values have to

be changed subsequently, i.e. during start-up, mode

change, etc., and while there is no picture visible on the

screen (blanked). The number of transmissions per

V-period is not limited.

Buffered mode

The buffered mode is selected by setting the MSB of the

I2C-bus register subaddress to logic 1.

This mode is designed to avoid visible interferences on the

screen during the I2C-bus adjustments. This mode should

be used, if a single register has to be changed while the

picture is visible, so i.e. for user adjustments.

One received I2C-bus data byte is stored in an internal

8-bit buffer before it is passed to the DAC section. The first

internal vertical blanking pulse (VBL) after end of

transmission is used to synchronize the adjustment

change with the vertical flyback. So the actual change of

the picture size, position, geometry, etc. will take place

during the vertical flyback period, and will thus be invisible.

The IC gives acknowledge for chip address, subaddress

and data of a buffered transmission. Only one I2C-bus

transmission is accepted after each vertical blank. After

one buffered transmission, the IC gives no acknowledge

for further transmissions until next VBL pulse has

occurred. The buffered mode is disabled while the IC is in

standby mode.

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