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TDA4841 Datasheet(PDF) 36 Page - NXP Semiconductors |
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TDA4841 Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 60 page  This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... List of I2C-bus controlled functions I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress: • SAD1 is the register subaddress to be used for transmissions in direct mode • SAD2 is the register subaddress to be used for transmissions in buffered mode. Table 6 Controlled functions; notes 1 and 2 FUNCTION NAME BITS SAD1 (HEX) SAD2 (HEX) REGISTER ASSIGNMENT CTRL BIT RANGE FUNCTION TRACKS WITH D7 D6 D5 D4 D3 D2 D1 D0 Horizontal size HSIZE 8 01 81 D7 D6 D5 D4 D3 D2 D1 D0 − 0.1 to 3.6 V − Horizontal position HPOS 8 07 87 D7 D6 D5 D4 D3 D2 D1 D0 −±13% of horizontal period − Horizontal pincushion HPIN 6 0F 8F X # D5 D4 D3 D2 D1 D0 − 0 to 1.42 V VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal trapezium correction HTRAP 6 03 83 X X D5 D4 D3 D2 D1 D0 −±500 mV (p-p) VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal corner correction at top of picture HCORT 6 04 84 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of parabola amplitude VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal corner correction at bottom of picture HCORB 6 02 82 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of parabola amplitude VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal parallelogram HPARAL 6 09 89 # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal period VSIZE, VOVSCN and VPOS EW pin balance HPINBAL 6 0B 8B # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal period VSIZE, VOVSCN and VPOS Vertical size VSIZE 7 08 88 # D6 D5 D4 D3 D2 D1 D0 − 60 to 100% VSMOD Vertical position VPOS 7 0D 8D X D6 D5 D4 D3 D2 D1 D0 −±11.5% VSMOD Vertical gain VGAIN 6 0A 8A X # D5 D4 D3 D2 D1 D0 70 to 100% − Vertical offset VOFFS 4 0E 8E #### D3 D2 D1 D0 ±4% − Vertical linearity VLIN 4 05 85 D7 D6 D5 D4 #### VSC −2to −46% VSIZE, VOVSCN, VPOS and VSMOD Vertical linearity balance VLINBAL 4 05 85 #### D3 D2 D1 D0 −±1.4% of 100% vertical size VSIZE, VOVSCN, VPOS and VSMOD |
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