M68HC08 datasheet(88/288 Pages) FREESCALE

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System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

System Integration Module (SIM)

Freescale Semiconductor

7.7.1

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7.7.2

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.8

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.8.1

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 108

7.8.2

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 109

7.8.3

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 110

7.2 Introduction

This section describes the system integration module, which supports up

to 16 external and/or internal interrupts. Together with the CPU, the SIM

controls all MCU activities. A block diagram of the SIM is shown in

Figure 7-1. Table 7-1 shows a summary of the SIM I/O registers. The

SIM is a system state controller that coordinates CPU and exception

timing. The SIM is responsible for:

•

Bus clock generation and control for CPU and peripherals:

–

Stop/wait/reset/break entry and recovery

–

Internal clock control

•

Master reset control, including power-on reset (POR) and COP

timeout

•

Interrupt control:

–

Acknowledge timing

–

Arbitration control timing

–

Vector address generation

•

CPU enable/disable timing

•

Modular architecture expandable to 128 interrupt sources

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