TDA8705 datasheet(8/16 Pages) PHILIPS

8 / 16 page

1996 Jan 12

Philips Semiconductors

Product speciﬁcation

6-bit high-speed dual Analog-to-Digital

Converter (ADC)

TDA8705

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 1 ns.

2. Analog input voltages producing code 00 up to and including 3F:

a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (VRB) at Tamb =25 °C.

b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to 3F at Tamb =25 °C.

3. Full-scale sine wave (fi = 10 MHz; fclk = 40 MHz).

4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both

ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE

(mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.

5. The

−0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a

full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB

× 6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.1 MHz. The two

input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

9. Output data acquisition: the output data is available after the maximum delay time of td.

BIT ERROR RATE

BER

bit error rate

fclk = 40 MHz;

fi = 10 MHz;

VI = ±16 LSB at code 32

−

10−13

−

times/

samples

Timing; fclk = 40 MHz; CL = 15 pF; note 9; see Fig.3

tds

sampling delay time

−−

2ns

output hold time

−−

output delay time

−−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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