 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TDA9605 Datasheet(PDF) 18 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
TDA9605 Datasheet(HTML) 18 Page - NXP Semiconductors |
|
|
18 / 52 page  1999 Apr 14 18 Philips Semiconductors Product specification Audio processor with head amplifier for VHS hi-fi TDA9605H 7I2C-BUS PROTOCOL 7.1 Addresses and data bytes Full control of the TDA9605H is accomplished via the 2-wire I2C-bus. Bus speeds up to 400 kbits/s can be used in accordance with the I2C-bus fast-mode specification. Seven data byte registers are available for programming the device (write mode) and one data byte register is available for reading data from the device (read mode). The registers are addressable via eight subaddresses. Automatic subaddress incrementing enables writing of successive data bytes in one transmission. During power-up, the data byte registers and auto-calibration registers are reset to a default state by the use of a Power-On Reset (POR) circuit. The reset signal is derived from an internally generated voltage supplied by VCC. Table 6 Addresses and POR state bits Notes 1. Continuous writing to a single data byte register is possible when subaddresses F0H to F7H (1111 0xxx) are used instead of 00H to 07H (0000 0xxx). In that case automatic subaddress incrementing is disabled. 2. It is advised to keep the not-used write bits equal to the POR state to accommodate future compatibility. 3. You cannot rely upon the state of the not-used read bits because their state may change during development. NAME ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write mode Slave byte B8H 10111000 Subaddress byte 00H to 07H; note 1 000000 or 1 0 or 1 0 or 1 Control byte subaddress 00H AFM DOC SHH DETH NTSC HAC2 HAC1 HAC0 POR state 10001000 Select byte subaddress 01H DOS1 DOS0 s5 HRL NIL3 NIL2 NIL1 NIL0 POR state 0 0 0(2) 00000 Input byte subaddress 02H i7 IS2 IS1 IS0 NS2 NS1 NS0 i0 POR state 0(2) 0001110(2) Output byte subaddress 03H LOH OSN OSR OSL EOS LOS DOS RFCM POR state 00000001 Left volume byte subaddress 04H l7 VLS VL5 VL4 VL3 VL2 VL1 VL0 POR state 0(2) 1000000 Right volume byte subaddress 05H r7 VRS VR5 VR4 VR3 VR2 VR1 VR0 POR state 0(2) 1000000 Volume byte subaddress 06H simultaneous loading of the subaddress 04H and subaddress 05H registers Power byte subaddress 07H CALS VCCS TEST PORR HPD MUTE STBP STBA POR state 00000100 Read mode Slave address byte B9H 10111001 Read byte B9H CALR AUTN CALE POR 0(3) 0(3) 0(3) 0(3) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
