3803 datasheet(11/119 Pages) RENESAS

11 / 119 page

Rev.1.00

Apr 2, 2007

Page 11 of 117

REJ03B0212-0100

3803 Group (Spec.L)

[Processor status register (PS)]

The processor status register is an 8-bit register consisting of 5

flags which indicate the status of the processor after an

arithmetic operation and 3 flags which decide MCU operation.

Branch operations can be performed by testing the Carry (C)

flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.

In decimal mode, the Z, V, N flags are not valid.

Bit 0: Carry flag (C)

The C flag contains a carry or borrow generated by the

arithmetic logic unit (ALU) immediately after an arithmetic

operation. It can also be changed by a shift or rotate

instruction.

Bit 1: Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic

operation or a data transfer is “0”, and cleared if the result is

anything other than “0”.

Bit 2: Interrupt disable flag (I)

The I flag disables all interrupts except for the interrupt

generated by the BRK instruction.

Interrupts are disabled when the I flag is “1”.

Bit 3: Decimal mode flag (D)

The D flag determines whether additions and subtractions are

executed in binary or decimal. Binary arithmetic is executed

when this flag is “0”; decimal arithmetic is executed when it

is “1”.

Decimal correction is automatic in decimal mode. Only the

ADC and SBC instructions can execute decimal arithmetic.

Bit 4: Break flag (B)

The B flag is used to indicate that the current interrupt was

generated by the BRK instruction. The BRK flag in the

processor status register is always “0”. When the BRK

instruction is used to generate an interrupt, the processor

status register is pushed onto the stack with the break flag set

to “1”.

Bit 5: Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed

between accumulator and memory. When the T flag is “1”,

direct arithmetic operations and direct data transfers are

enabled between memory locations.

Bit 6: Overflow flag (V)

The V flag is used during the addition or subtraction of one

byte of signed data. It is set if the result exceeds +127 to

−

128. When the BIT instruction is executed, bit 6 of the

memory location operated on by the BIT instruction is stored

in the overflow flag.

Bit 7: Negative flag (N)

The N flag is set if the result of an arithmetic operation or

data transfer is negative. When the BIT instruction is

executed, bit 7 of the memory location operated on by the

BIT instruction is stored in the negative flag.

Table 5

Set and clear instructions of each bit of processor status register

C flag

Z flag

I flag

D flag

B flag

T flag

V flag

N flag

Set instruction

SEC

−

SEI

SED

−

SET

−−

Clear instruction

CLC

−

CLI

CLD

−

CLT

CLV

−

3803 Datasheet(PDF) 11 Page - Renesas Technology Corp

3803 Datasheet(HTML) 11 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL