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3803 Datasheet(PDF) 29 Page - Renesas Technology Corp |
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3803 Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 119 page  Rev.1.00 Apr 2, 2007 Page 29 of 117 REJ03B0212-0100 3803 Group (Spec.L) Fig 24. Timing of interrupt request generation, interrupt request bit, and interrupt acceptance T1 (1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1. (2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2. The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately. T1 T2 T3 : Interrupt acceptance timing points IR1 IR2 : Timings points at which the interrupt request bit is set to “1”. Note : Period 2 indicates the last φ cycle during one instruction cycle. IR1 T2 SYNC IR2 T3 12 Internal clock φ Instruction cycle Push onto stack Vector fetch Instruction cycle |
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