3803 datasheet(13/119 Pages) RENESAS

13 / 119 page

Rev.1.00

Apr 2, 2007

Page 13 of 117

REJ03B0212-0100

3803 Group (Spec.L)

MISRG

(1) Bit 0 of address 001016: Oscillation stabilizing time

set after STP instruction released bit

When the MCU stops the clock oscillation by the STP instruction

and the STP instruction has been released by an external

interrupt source, usually, the fixed values of Timer 1 and

Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are

automatically reloaded in order for the oscillation to stabilize.

The user can inhibit the automatic setting by setting “1” to bit 0

of MISRG (address 001016).

However, by setting this bit to “1”, the previous values, set just

before the STP instruction was executed, will remain in Timer 1

and Prescaler 12. Therefore, you will need to set an appropriate

value to each register, in accordance with the oscillation

stabilizing time, before executing the STP instruction.

Figure 10 shows the structure of MISRG.

(2) Bits 1, 2, 3 of address 001016: Middle-speed Mode

Automatic Switch Function

In order to switch the clock mode of an MCU which has a sub-

clock, the following procedure is necessary:

set CPU mode register (003B16) --> start main clock oscillation

--> wait for oscillation stabilization --> switch to middle-speed

mode (or high-speed mode).

However, the 3803 group (Spec.L) has the built-in function

which automatically switches from low to middle-speed mode by

program.

• Middle-speed mode automatic switch by program

The middle-speed mode can also be automatically switched by

program while operating in low-speed mode. By setting the

middle-speed automatic switch start bit (bit 3) of MISRG

(address 001016) to “1” in the condition that the middle-speed

mode automatic switch set bit is “1” while operating in low-

speed mode, the MCU will automatically switch to middle-speed

mode. In this case, the oscillation stabilizing time of the main

clock can be selected by the middle-speed automatic switch wait

time set bit (bit 2) of MISRG (address 001016).

Fig 10. Structure of MISRG

MISRG

(MISRG: address 001016)

Oscillation stabilizing time set after STP instruction

released bit

0 : Automatically set “0116” to Timer 1, “FF16” to

Prescaler 12

1 : Automatically set disabled

Middle-speed mode automatic switch set bit

0 : Not set automatically

1 : Automatic switching enabled(1)

Middle-speed mode automatic switch wait time set bit

0 : 4.5 to 5.5 machine cycles

1 : 6.5 to 7.5 machine cycles

Middle-speed mode automatic switch start bit

(Depending on program)

0 : Invalid

1 : Automatic switch start(1)

Not used (return “0” when read)

(Do not write “1” to this bit)

Note 1 : When automatic switch to middle-speed mode from low-speed mode occurs,

the values of CPU mode register (3B16) change.

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