MAX8545 datasheet(13/18 Pages) MAXIM

13 / 18 page

Low-Cost, Wide Input Range, Step-Down

Controllers with Foldback Current Limit

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has a gain drop of 40dB per decade, and a phase shift

of 180°. The error amplifier must compensate for this

gain drop and phase shift to achieve a stable high-

bandwidth, closed-loop system.

The basic regulator loop consists of a power modulator

(Figure 3), an output feedback divider, and an error

amplifier. The power modulator has DC gain set by

VIN/VRAMP, with a double pole set by the inductor and

output capacitor, and a single zero set by the output

capacitor (COUT) and its equivalent series resistance

(ESR). Below are equations that define the power mod-

ulator:

The DC gain of the power modulator is:

where VRAMP = 1V.

The pole frequency due to the inductor and output

capacitor is:

The zero frequency due to the output capacitor’s ESR is:

The output capacitor is usually comprised of several

same capacitors connected in parallel. With n capaci-

tors in parallel, the output capacitance is:

COUT = n X CEACH

The total ESR is:

The ESR zero (fZESR) for a parallel combination of

capacitors is the same as for an individual capacitor.

The feedback divider has a gain of GFB = VFB/VOUT,

where VFB is 0.8V.

The transconductance error amplifier has DC gain

GEA(dc) of 72dB. A dominant pole (fDPEA) is set by the

compensation capacitor (CC), the amplifier output

resistance (RO) equals 37MΩ, and the compensation

resistor (RC):

The compensation resistor and the compensation

capacitor set a zero:

The total closed-loop gain must equal unity at the

crossover frequency. The crossover frequency should

be higher than fZESR, so that the -1 slope is used to

cross over at unity gain. Also, the crossover frequency

should be less than or equal to 1/5 the switching fre-

quency (fSW) of the controller:

The loop-gain equation at the crossover frequency is:

VFB/VOUT x GEA(fC) x GMOD(fC) = 1

where GEA(fC) = gmEA × RC, and GMOD(fC) =

GMOD(DC) × (fPMOD)2 / (fZESR × fC).

The compensation resistor, RC, is calculated from:

RC = VOUT/ gmEA x VFB x GMOD(fC)

where gmEA = 108µS.

Due to the underdamped (Q > 1) nature of the output

LC double pole, the error-amplifier compensation zero

should be approximately 0.2 fPMOD to provide good

phase boost. CC is calculated from:

A small capacitor, CF, can also be added from COMP to

GND to provide high-frequency decoupling. CF adds

another high-frequency pole, fPHF, to the error-amplifier

response. This pole should be greater than 100 times the

error-amplifier zero frequency to have negligible impact

on the phase margin. This pole should also be less than

1/2 the switching frequency for effective decoupling:

100 fZEA < fPHF < 0.5 fsw

Select a value for fPHF in the range given above, then

solve for CF using the following equation:

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and stable operation. If possible, mount all the

power components on the top side of the board with their

PHF

××

2π

PMOD

××

2π

ZESR

≤

ZEA

××

2π

DPEA

××

()

2π

ESR

EACH

ESR C

ZESR

OUT

××

2π

PMOD

OUT

2π

MOD DC

RAMP

() =

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