TDA9875 datasheet(84/92 Pages) PHILIPS

84 / 92 page

1998 Feb 13

Philips Semiconductors

Preliminary speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9875

loudspeaker and/or headphone channels. Apart from such

simple data input or output, it is also possible to run audio

signals through an external DSP, which performs some

additional functions, such as room simulation, Dolby

Surround Pro Logic etc. and feed those signals back into

the loudspeaker and/or headphone channels of the

TDA9875.

Two serial audio formats are supported at the feature

interface, i.e. the I2S-bus format and a very similar

MSB-aligned format. The difference is illustrated in Fig.7.

In both formats the left audio channel of a stereo sample

pair is output first and is placed on the serial data line (SDI

for input, SDO for output) when the word select line (WS)

is LOW. Data is written at the trailing edge of SCK and

read at the leading edge of SCK. The most significant bit

is sent first.

At power-up, the outputs of the feature interface are

3-stated to reduce EMC and allow for combinations with

other ICs. If output is desired, it has to be activated by

means of an I2C-bus command.

When the output is enabled, the serial audio data can be

taken from pins SDO1 and SDO2. Depending on the signal

source, switch and matrix positions, the output can be

either mono, stereo or dual language sound on either

output.

The word select output is clocked with the audio sample

frequency at 32 kHz. The serial clock output (SCK) is

clocked at a frequency of 2.048 MHz. This means, that

there are 64 clock pulses per pair of stereo output

samples, or 32 clock pulses per sample. Depending again

on the signal source, the number of significant bits on the

serial data outputs, SDO1 and SDO2, is between

14 and 18.

Apart from just feeding a digital audio device, such as a

DAC or an AES/EBU transmitter, the serial data outputs

can be connected directly to the serial inputs (loop-back

connection) or first to an external device, e.g. a feature

DSP such as the SAA7710 and then back to the serial

inputs. In all of these configurations, the SCK and WS

clocks will be generated by the TDA9875, which then is the

I2S-bus master.

The serial data inputs, SDI1 and SDI2, are active at all

times, independent of the serial data outputs being on or

off.

When the serial data outputs are off (either after power-up

or via the appropriate I2C-bus command) serial data and

clocks WS and SCK from a separate digital audio source

can be fed into the TDA9875, be processed and output in

accordance with internal selector positions, provided that

the following criteria are met:

• 32 kHz audio sample frequency

• 32 clock bits per sample

• External timing and data synchronized to TDA9875.

In such cases, the external source is the I2S-bus master

and the TDA9875 is the I2S-bus slave.

To support synchronization of external devices or as a

master clock for them, a symmetrical system clock output,

SYSCLK, is available from the TDA9875. At power-up it is

off. It can be enabled and the output frequency set via an

I2C-bus command. Available output frequencies are

8.192, 12.288, 16.384 and 24.576 MHz.

TDA9875 Datasheet(PDF) 84 Page - NXP Semiconductors

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