TUSB8020BPHPR datasheet(16/44 Pages) TI

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TUSB8020B

SLLSEF6C – JULY 2014 – REVISED JUNE 2017

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8.5.1.6 Device Configuration Register (offset = 5h) [reset = 1Xh]

Figure 8. Register Offset 5h

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 9. Device Configuration Register

Bit

Field

Type

Reset

Description

customStrings

R/W

1Xh

Custom strings enable. This bit controls the ability to write to the Manufacturer String

Length, Manufacturer String, Product String Length, Product String, and Language ID

registers.

0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product

String, and Language ID registers are read only.

1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product

String, and Language ID registers may be loaded by EEPROM or written by SMBus.

The default value of this bit is 0.

customSernum

R/W

1Xh

Custom serial number enable. This bit controls the ability to write to the serial number

registers.

0 = The Serial Number String Length and Serial Number String registers are read only.

1 = The Serial Number String Length and Serial Number String registers may be loaded

by EEPROM or written by SMBus.

The default value of this bit is 0.

u1u2Disable

R/W

1Xh

U1 U2 Disable. This bit controls the U1/U2 support.

0 = U1/U2 support is enabled.

1 = U1/U2 support is disabled, the TUSB8020B does not initiate or accept any U1 or U2

requests on any port, upstream or downstream, unless it receives or sends a

Force_LinkPM_Accept LMP. After receiving or sending an FLPMA LMP, it continues to

enable U1 and U2 according to USB 3.0 protocol until it gets a power-on reset or is

disconnected on its upstream port.

When the TUSB8020B is in I2C mode, the TUSB8020B loads this bit from the contents of

the EEPROM.

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

RSVD

1Xh

Reserved. This bit is reserved and returns 1 when read.

ganged

R/W

1Xh

Ganged. This bit is loaded at the deassertion of reset with the value of the

GANGED/SMBA2/HS_UP terminal.

0 = When fullPwrMgmtz = 0, each port is individually power switched and enabled by the

PWRCTL[2:1]/BATEN[2:1] terminals

1 = When fullPwrMgmtz = 0, the power switch control for all ports is ganged and enabled

by the PWRCTL1/BATEN1 terminal

When the TUSB8020B is in I2C mode, the TUSB8020B loads this bit from the contents of

the EEPROM.

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

fullPwrMgmtz

R/W

1Xh

Full Power Management. This bit is loaded at the deassertion of reset with the value of

the FULLPWRMGMTz/SMBA1/SS_UP terminal.

0 = Port power switching and over-current status reporting is enabled

1 = Port power switching and over-current status reporting is disabled

When the TUSB8020B is in I2C mode, the TUSB8020B loads this bit from the contents of

the EEPROM.

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

RSVD

R/W

1Xh

Reserved. This bit is reserved and should not be altered from the default.

RSVD

1Xh

Reserved. This field is reserved and returns 0 when read.

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