UDA1328 datasheet(13/28 Pages) PHILIPS

13 / 28 page

2000 Jan 04

Philips Semiconductors

Preliminary speciﬁcation

Multi-channel ﬁlter DAC

UDA1328T

Table 6

Data transfer of type ‘status’

Table 7

Data transfer of type ‘data’

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RST

SC1

SC0

IF2

IF1

IF0

ReSeT

System Clock frequency (1 and 0)

data Input Format (2 to 0)

100000

Quick/soft Mute

Power Control

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

VC5

VC4

VC3

VC2

VC1

VC0

Volume Control (5 to 0)

010000

VQ1

VQ0

0.25 dB step sub volume (1 and 0)

DE2

DE1

DE0

DSM

PLC

DE-emphasis (2 to 0)

MuTe

Digital Silence Mode

PoLarity Control

1100

ACH

CH2

CH1

CH0

All CHannels select

CHannel select (2 to 0)

Fig.8 Multibyte transfer.

handbook, full pagewidth

tstp(L3)

address

L3DATA

L3CLOCK

L3MODE

address

data byte #1

data byte #2

MGL725

UDA1328 Datasheet(PDF) 13 Page - NXP Semiconductors

UDA1328 Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL