MP6908- FAST TURN-OFF INTELLIGENT RECTIFIER

MP6908 Rev. 1.2

www.MonolithicPower.com

11

9/14/2021

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Figure 6-A shows HVC connected to VD. Here,

VDD

is

generated

and

regulated

at

9V.

VD

VSS

SLEW

VG

HVC

VDD

MP6908

Figure 6-A: High-Side Rectification, VDD

Regulated at 9V

Figure 6-B shows HVC connected to the

secondary ground through an external diode.

Here,

VDD

is

generated

from

HVC

and

regulated at 9V. The maximum voltage at HVC

can be calculated with Equation (2):

p

s

IN

HVC

N

N

V

V





(max)

(2)

VD

VSS

SLEW

VG

HVC

VDD

MP6908

Figure 6-B: High-Side Rectification, VDD

Regulated at 9V

HVC works the same as described above when

VHVC is below 4.7V since HVC is shorted to VSS

(see Figure 7). Here, VDD is generated by VDS

and regulated at 5V.

VD

VSS

SLEW

VG

HVC

VDD

MP6908

Figure 7: High-Side Rectification, VDD Regulated

at 5V

SR MOSFET Selection

Power MOSFET selection is a tradeoff between

the RDS(ON) and QG. To achieve higher efficiency,

the

MOSFET

with

the

smaller

RDS(ON) is

preferred. Typically, QG is usually larger with a

smaller RDS(ON), which makes the turn-on/turn-

off speed lower and leads to larger power loss

and driver loss. Because VDS is adjusted at

about -40mV during the driving period when the

switching current is fairly small, a MOSFET with

an RDS(ON) that is too low is not recommended

because the gate driver is pulled low when VDS

= -ISD x RDS(ON) becomes larger than -40mV.

The MOSFET

’s RDS(ON) does not contribute to

the conduction loss. The conduction loss is

PCON = -VDS x ISD ≈ ISD x 40mV.

To achieve fairly high use of the MOSFET

’s

RDS(ON), the MOSFET should be turned on

completely

for

at

least

50%

of

the

SR

conduction period. Calculate VDS with Equation

(3):

fwd

ON

DS

OUT

ON

DS

C

DS

V

R

D

I

R

I

V

















)

(

)

(

/

(3)

Where VDS is drain-source voltage of the

MOSFET, D is the duty cycle of the secondary

side, IOUT is output current, and Vfwd is the

forward voltage threshold (~40mV).

Figure 8 shows the typical waveform of a

flyback application. Assume it has a 50% duty

cycle. The MOSFET

’s RDS(ON) is recommended

to be no lower than ~20/IOUT (mΩ). For example.

for a 5A application, the RDS(ON) should be no

lower than 4m

Ω.

Ipeak

SR Conduction Period

50% SR Conduction

Period

Ic

VGS

Ivalley

Ic≈(Ipeak+Ivalley)/2

IOUT≈Ic·D

ISD

Figure 8: Synchronous Rectification Typical

Waveforms in a Flyback Application

PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation. For best results, refer to Figure 9,

Figure 10, Figure 11, and follow the guidelines

below.