MP6908- FAST TURN-OFF INTELLIGENT RECTIFIER

MP6908 Rev. 1.2

www.MonolithicPower.com

12

9/14/2021

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Sensing for VD/VSS

1. Make the sensing connection (VD/VSS) as

close

as

possible

to

the

MOSFET

(drain/source).

2. Make the sensing loop as small as possible.

3. Keep the IC out of the power loop to prevent

the sensing loop and power loop from

interrupting each other (see Figure 9).

VD

VSS

G

D

S

Sensing loops separated

from power loop

Sensing loop as

small as

possible

Figure 9: Voltage Sensing for VD/VSS

4. Place a decoupling ceramic capacitor from

VDD to PGND close to the IC for adequate

filtering.

Gate Driver Loop

1. Make the gate driver loop as small as

possible

to

minimize

the

parasitic

inductance.

2. Keep the driver signal far away from the VD

sensing trace on the layout.

Layout Example

Figure 10 shows a layout example of a single

layer with a through-hole transformer and a

TO220 package SR MOSFET. RSN and CSN

are the RC snubber network for the SR

MOSFET. The sensing loop (VD and VSS to

the SR MOSFET) is minimized and kept

separate from the power loop. The VDD

decoupling capacitor (C2) is placed beside VDD.

Figure 11 shows another layout example of a

single layer with a PowerPAK/SO8 package SR

MOSFET, which also has a minimized sensing

loop and power loop to prevent the loops from

interfering with one another.

G

D

S

Q1

U1

R1

C2

R2

C1

RSN

CSN

LAYOUT TRACE

COMPONENTS PAD

JUMP WIRE

4

5

6

2

3

1

Figure 10: Layout Example with TO220 Package

SR MOSFET

Q1

R2

U1

R1

C2

LAYOUT TRACE

COMPONENTS PAD

JUMP WIRE

C1

RSN

CSN

Figure 11: Layout Example with PowerPAK/SO8

SR MOSFET