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S29GL01GS Datasheet(PDF) 88 Page - Infineon Technologies AG

Part # S29GL01GS
Description  128 Mb/256 Mb/512 Mb/1 Gb GL-S MIRRORBIT™ flash Parallel, 3.0 V
PDF  122 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

S29GL01GS Datasheet(HTML) 88 Page - Infineon Technologies AG

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Datasheet
88
001-98285 Rev. *U
2024-06-25
128 Mb/256 Mb/512 Mb/1 Gb GL-S MIRRORBIT™ flash
Parallel, 3.0 V
Timing specifications
11.3.2
Hardware (Warm) Reset
During Hardware Reset (tRPH) the device will draw ICC5 current.
When RESET# continues to be held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL,
but not at VSS, the standby current is greater.
If a Cold Reset has not been completed by the device when RESET# is asserted LOW after tVCS, the Cold Reset# EA
will be performed instead of the Warm RESET#, requiring tVCS time to complete.
See Figure 16.
After the device has completed POR and entered the Standby state, any later transition to the Hardware Reset
state will initiate the Warm Reset Embedded Algorithm. A Warm Reset is much shorter than a Cold Reset, taking
tens of µs (tRPH) to complete. During the Warm Reset EA, any in progress Embedded Algorithm is stopped and the
EAC is returned to its POR state without reloading EAC algorithms from non-volatile memory. After the Warm
Reset EA completes, the interface will remain in the Hardware Reset state if RESET# remains LOW. When RESET#
returns HIGH the interface will transit to the Standby state. If RESET# is HIGH at the end of the Warm Reset EA,
the interface will directly transit to the Standby state.
If POR has not been properly completed by the end of tVCS, a latertransition to theHardware Reset state will cause
a transition to the Power-on Reset interface state and initiate the Cold Reset Embedded Algorithm. This ensures
the device can complete a Cold Reset even if some aspect of the system Power-On voltage ramp-up causes the
POR to not initiate or complete correctly. The RY/BY# pin is LOW during cold or warm reset as an indication that
the device is busy performing reset operations.
Hardware Reset is initiated by the RESET# signal going to VIL.
Figure 16
Hardware Reset
RESET#
CE#
tRP
tRPH
tRH
tCEH



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