RT1060 datasheet(71/119 Pages) NXP

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Electrical Characteristics

i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024

NXP Semiconductors

Figure 39. LPSPI Master mode timing (CPHA = 0)

Table 57. LPSPI Master mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

—

fperiph / 2

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be

guaranteed this limit is not exceeded.

tSCK

SCK period

2 x tperiph

—

2 tperiph = 1 / fperiph

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSCK

Clock (SCK) high or low time

tSCK / 2 - 3

—

tSU

Data setup time (inputs) with SAMPLE set to

—

3 SAMPLE is a bit field in register CFGR1, See the i.MX RT1060 Reference Manual (IMXRT1060RM) for further details.

Data setup time (inputs) with SAMPLE set to

2.7

—

tHI

Data hold time (inputs)

—

Data valid (after SCK edge)

—

tHO

Data hold time (outputs)

—

(OUTPUT)

MSB IN

LSB IN

MSB OUT

LSB OUT

(CPOL=0)

SCK

(CPOL=1)

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

PCS

(OUTPUT)

SOUT

(OUTPUT)

SIN

(INPUT)

BIT 6 . . . 1

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