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PM73122 Datasheet(PDF) 39 Page - PMC-Sierra, Inc

Part # PM73122
Description  32 LINK CES/DBCES AAL1 SAR PROCESSOR
PDF  489 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73122 Datasheet(HTML) 39 Page - PMC-Sierra, Inc

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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
7
BLOCK DIAGRAM
The AAL1gator-32 contains four AAL1 SAR Processors (A1SP) which work in
parallel. The A1SP blocks interface to a common UTOPIA interface on one side
and a Line Interface block on the other side which can be configured to support
several different line protocols. Two of the A1SP blocks share one ram interface
and the other two A1SP blocks share the other ram interface. The processor
Interface block which also contains the external clock control interface is shared
by all blocks.
Figure 4 AAL1gator-32 Internal Block Diagram
Clock
MUX
JTAG
RAM2
Interface
RAM 1
Interface
UTOPIA
Interface
Processor
Interface
External Clock
Interface
SBI
H-MVIP
Low Speed
High Speed
TATM_DATA[15:0]
TATM_PAR
TATM_ENB
TATM_SOC
TATM_CLAV
TATM_CLK
RPHY_ADD[4:0]
RATM_DATA[15:0]
RATM_PAR
RATM_ENB
RATM_SOC
RATM_CLAV
RATM_CLK
TPHY_ADD[4:0]
LINE_MODE[1:0]
ADETECT
AACTIVE
REFCLK
C1FP
DDATA[7:0]
DDP
DPL
DV5
ADATA[7:0]
ADP
AJUST_REQ
APL
AV5
F0B
TL_DATA[15:0]
TL_SYNC[15:0]
TL_SIG[15:0]
RL_DATA[15:0]
RL_SYNC[15:0]
RL_SIG[15:0]
RSTB
SCAN_ENB
SCAN_MODEB
16
2
8
32
16
2
32
32
8
8
8
8
A1SP
A1SP
A1SP
A1SP
8
8
8
8
Line Interface



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