PM7324 datasheet(21/473 Pages) PMC

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S/UNI-ATLAS

PM7324 S/UNI-ATLAS

DATASHEET

PMC-1971154

ISSUE 7

S/UNI-ATM LAYER SOLUTION

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

RRDENB[1]

RRDENB[2]

RRDENB[3]

RRDENB[4]

Output

The active low read enable (RRDENB[4:1]) outputs are used to

initiate the reading of cells from a PHY device into the Ingress

Input Cell Interface.

If the RPOLL pin is low, the ATLAS asserts one of the

RRDENB[4:1] outputs to transfer a cell from one of up to 4 PHY

devices. A valid word is expected on the RDAT[15:0] bus at the

second rising edge of RFCLK after one of the enables is

asserted. When all of the enables are deasserted, no valid data

is expected.

The RRDENB[4:1] outputs are updated on the rising edge of

RFCLK.

If the RPOLL pin is high, the RRDENB[4:2] pins are redefined as

RADDR[2:0]. The RRDENB[1] pin is used to transfer all cells.

The source PHY is selected by the RADDR[4:0] signals.

RADDR[4]

RADDR[3]

RADDR[2]

RADDR[1]

RADDR[0]

Output

If the RPOLL pin is high, the RADDR[4:0] pins are used for PHY

addressing. If the RPOLL pin is low, the RADDR[4:0] pins are

redefined as RCA[3:2] and RRDENB[4:2].

If the RPOLL pin is high, the RADDR[4:0] signals are used to

address up to 32 PHY devices for the purposes of polling and

selection for cell transfer. When conducting polling, in order to

avoid bus contention, the ATLAS inserts gap cycles during which

RADDR[4:0] is set to 0x1F and RAVALID is logic 0. When this

occurs, no PHY device should drive RCA[1] during the following

clock cycle. Polling is performed in incrementing sequential

order. The PHY device selected for transfer is based on the

RADDR[4:0] value present when RRDENB[1] is falls. The

RADDR[4:0] bus is updated on the rising edge of RFCLK.

RAVALID

I/O

If the RPOLL pin is high, the PHY Address Valid (RAVALID) pin is

active. If the RPOLL pin is low, the RAVALID pin is redefined as

RCA[4].

If the RPOLL pin is high, the RAVALID pin indicates that the

RADDR[4:0] bus is asserting a valid PHY address for polling

purposes. When this signal is deasserted, the RADDR[4:0] bus

is set to 0x1F.

RAVALID is not necessary when less than 32 PHY devices are

being polled. RAVALID is updated on the rising edge of RFCLK.

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