PM7324 datasheet(39/473 Pages) PMC

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S/UNI-ATLAS

PM7324 S/UNI-ATLAS

DATASHEET

PMC-1971154

ISSUE 7

S/UNI-ATM LAYER SOLUTION

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

ESD[15]

ESD[14]

ESD[13]

ESD[12]

ESD[11]

ESD[10]

ESD[9]

ESD[8]

ESD[7]

ESD[6]

ESD[5]

ESD[4]

ESD[3]

ESD[2]

ESD[1]

ESD[0]

I/O

A13

B13

C13

A12

B12

D13

C12

A11

B11

D12

C11

A10

B10

D11

C10

Continued

ESP[3]

ESP[2]

ESP[1]

ESP[0]

I/O

D19

B20

A20

C19

The Egress VC Table SRAM parity (ESP[3:0]) pins provide parity

protection over the ESD[31:0] data bus.

ESP[0] completes the odd parity for ESD[7:0]

ESP[1] completes the odd parity for ESD[15:8]

ESP[2] completes the odd parity for ESD[23:16]

ESP[3] completes the odd parity for ESD[31:24]

ESP[3:0] has the same timing as ESD[31:0]. When data are

being written into the SRAM, the ATLAS generates correct parity.

When data are being read from the SRAM, the ATLAS asserts a

maskable interrupt indication upon parity error detection. No

other action is taken, therefore, the ESP[3:0] may be

unconnected if parity protection is not required.

PM7324 Datasheet(PDF) 39 Page - PMC-Sierra, Inc

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