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PM7340-PI Datasheet(PDF) 35 Page - PMC-Sierra, Inc |
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PM7340-PI Datasheet(HTML) 35 Page - PMC-Sierra, Inc |
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35 / 334 page ![]() PRELIMINARY INVERSE MULTIPLEXING OVER ATM PM7340 S/UNI-IMA-8 DATA SHEET PMC-2001723 ISSUE 3 INVERSE MULTIPLEXING OVER ATM PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18 Pin Name Type Pin No. Function RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] Output U22 T22 U19 R20 R22 T19 R19 P20 P21 P22 P19 N20 N21 N22 N19 M20 The Receive Cell Data (RDAT[15:0]) signals carry the ATM cell words that have been read from the S/UNI-IMA-8 internal cell buffers. When this interface is operating in 8-bit mode, the data is carried on RDAT[7:0]. The RDAT[15:0] output bus is updated on the rising edge of RCLK. RPRTY Output M22 The Receive Parity (RPRTY) signal provides the parity (programmable for odd or even parity) of the RDAT[15:0] bus. When the interface is operating in 8-bit mode, the parity is calculated over RDAT[7:0] The RPRTY output is updated on the rising edge of RCLK. 9.1 Receive Slave ATM Interface (UTOPIA L2 mode) (26 Signals) Pin Name Type Pin No. Function RCLK Input T21 The Receive Clock (RCLK) signal is used to transfer data blocks from the S/UNI-IMA-8 across the receive UTOPIA L2 interface. The RCA, RSOC, RDAT[15:0], and RPRTY outputs are updated on the rising edge of RCLK. The RENB and RADR[4:0] inputs are sampled on the rising edge of RCLK. The RCLK input must cycle at a 52 MHz or lower instantaneous rate. |
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