PM7366-PI datasheet(194/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

181

The HDLC processor starts transmitting a packet when the channel FIFO free space is less

than or equal to the level specified in the appropriate Start Transmission Level column of the

following table or when an end of a packet is stored in the channel FIFO. When the channel

FIFO free space is less than or equal to the level specified in the Expedite Trigger Level

column of the following table and the HDLC processor is transmitting a packet and an end of

a packet is not stored in the channel FIFO, the partial packet buffer makes expedite requests

to the TMAC to retrieve XFER[2:0] + 1 blocks of data.

To prevent lockup, the channel transfer size (XFER[2:0]) can be configured to be less than or

equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel

transfer size can be set, such that, the total number of blocks in the logical channel FIFO

minus the start transmission level is an integer multiple of the channel transfer size.

TRANS:

The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0] bits, configure the

various channel FIFO free space levels which trigger the HDLC processor to start

transmission of a HDLC packet as well as trigger the partial packet buffer to make DMA

request for data as shown in the following table. The transmission start mode to be written to

the channel provision RAM, in an indirect write operation, must be set up in this register

before triggering the write. TRANS reflects the value written until the completion of a

subsequent indirect channel read operation.

The HDLC processor starts transmitting a packet when the channel FIFO free space is less

than or equal to the level specified in the appropriate Start Transmission Level column of the

following table or when an end of a packet is stored in the channel FIFO. When the channel

FIFO free space is greater than the level specified in the Expedite Trigger Level column of the

following table and the HDLC processor is transmitting a packet and an end of a packet is not

stored in the channel FIFO, the partial packet buffer makes expedited requests to the TMAC

to retrieve XFER[2:0] + 1 blocks of data.

To prevent lockup, the channel transfer size (XFER[2:0]) can be configured to be less than or

equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel

transfer size can be set, such that, the total number of blocks in the logical channel FIFO

minus the start transmission level is an integer multiple of the channel transfer size.

Table 26 – Level[3:0]/TRANS Settings

LEVEL[3:0]

Expedite

Trigger Level

Start Transmission

Level (TRANS=0)

Start Transmission

Level (TRANS=1)

0000

2 Blocks

(32 bytes free)

1 Block

(16 bytes free)

1 Block

(16 bytes free)

0001

3 Blocks

(48 bytes free)

2 Blocks

(32 bytes free)

1 Block

(16 bytes free)

0010

4 Blocks

(64 bytes free)

3 Blocks

(48 bytes free)

2 Blocks

(32 bytes free)

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