PM7366-PI datasheet(28/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Table 2 – PCI Host Interface Signals (51)

Pin No.

Pin Name

Type

-PI

-BI

Function

PCICLK

Input

B17

The PCI clock signal (PCICLK) provides timing for

PCI bus accesses. PCICLK is a nominally 50% duty

cycle, 0 to 33 MHz clock.

PCICLKO

Output

C17

The PCI clock output signal (PCICLKO) is a buffered

version of the PCICLK. PCICLKO may be used to

drive the SYSCLK input.

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

AD[5]

AD[6]

AD[7]

AD[8]

AD[9]

AD[10]

AD[11]

AD[12]

AD[13]

AD[14]

AD[15]

AD[16]

AD[17]

AD[18]

AD[19]

AD[20]

AD[21]

AD[22]

AD[23]

AD[24]

AD[25]

AD[26]

AD[27]

AD[28]

AD[29]

AD[30]

I/O

U19

U18

T17

U20

T18

T19

T20

R18

R20

P18

P19

P20

N18

N19

N20

M17

J19

J18

J17

H20

H19

H18

G20

G19

F19

E20

G17

F18

E19

D20

E18

The PCI address and data bus (AD[31:0]) carries the

PCI bus multiplexed address and data. During the

first clock cycle of a transaction, AD[31:0] contains a

physical byte address. During subsequent clock

cycles of a transaction, AD[31:0] contains data.

A transaction is defined as an address phase followed

by one or more data phases. When Little-Endian

byte formatting is selected, AD[31:24] contain the

most significant byte of a DWORD while AD[7:0]

contain the least significant byte. When Big-Endian

byte formatting is selected. AD[7:0] contain the most

significant byte of a DWORD while AD[31:24] contain

the least significant byte. When the FREEDM-8 is the

initiator, AD[31:0] is an output bus during the first

(address) phase of a transaction. For write

transactions, AD[31:0] remains an output bus for the

data phases of the transaction. For read

transactions, AD[31:0] is an input bus during the data

phases.

When the FREEDM-8 is the target, AD[31:0] is an

input bus during the first (address) phase of a

transaction. For write transactions, AD[31:0] remains

an input bus during the data phases of the

transaction. For read transactions, AD[31:0] is an

output bus during the data phases.

When the FREEDM-8 is not involved in the current

transaction, AD[31:0] is tri-stated.

PM7366-PI Datasheet(PDF) 28 Page - PMC-Sierra, Inc

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