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PM7366-PI Datasheet(PDF) 96 Page - PMC-Sierra, Inc

Part # PM7366-PI
Description  FRAME ENGINE AND DATA LINK MANAGER
PDF  286 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7366-PI Datasheet(HTML) 96 Page - PMC-Sierra, Inc

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RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83
Register 0x008 : FREEDM-8 Master Interrupt Status
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R
TFUDRI
X
Bit 14
R
IOCI
X
Bit 13
R
TDFQEI
X
Bit 12
R
TDQRDYI
X
Bit 11
R
TDQFI
X
Bit 10
R
RPDRQEI
X
Bit 9
R
RPDFQEI
X
Bit 8
R
RPQRDYI
X
Bit 7
R
RPQLFI
X
Bit 6
R
RPQSFI
X
Bit 5
R
RFOVRI
X
Bit 4
R
RPFEI
X
Bit 3
R
RABRTI
X
Bit 2
R
RFCSEI
X
Bit 1
R
PERRI
X
Bit 0
R
SERRI
X
This register reports the interrupt status for various events detected or initiated by the FREEDM.
Reading this registers acknowledges and clears the interrupts.
Note
This register is not byte addressable. Reading this register clears all the interrupt bits in the
register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However,
when all four byte enables are negated, no access is made to this register.
SERRI:
The system error interrupt status bit (SERRI) reports PCI system error interrupts to the PCI
host. SERRI is set high upon detection of any address parity error, data parity error on
Special Cycle commands, reception of a master abort or detection of a target abort event.



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