PM7366-PI datasheet(90/286 Pages) PMC

90 / 286 page

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Bit

Type

Function

Default

Bit 31

Bit 16

Unused

XXXXH

Bit 15

R/W

Reset

Bit 14

Unused

Bit 13

Unused

Bit 12

Unused

Bit 11

Unused

Bit 10

Unused

Bit 9

Unused

Bit 8

Unused

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

Unused

Bit 0

Unused

This register provides software reset capability.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

RESET:

The RESET bit allows the FREEDM-8 to be reset under software control. If the RESET bit is

a logic one, the entire FREEDM-8 except the PCI Interface is held in reset. This bit is not

self-clearing. Therefore, a logic zero must be written to bring the FREEDM-8 out of reset.

PM7366-PI Datasheet(PDF) 90 Page - PMC-Sierra, Inc

PM7366-PI Datasheet(HTML) 90 Page - PMC-Sierra, Inc

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