PM7366-PI datasheet(80/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

elements of the end of the free queue. If the write pointer is near the end of the free queue, the

cache controller writes only to the end of the queue and does not start writing from the top of the

queue until the next time a flush is required. To do so would require two host memory

transactions and would be of no benefit.

9.7

Transmit HDLC Controller / Partial Packet Buffer

The Transmit HDLC Controller / Partial Packet Buffer block (THDL) contains a partial packet

buffer for PCI latency control and a transmit HDLC controller. Packet data retrieved from the PCI

host memory by the Transmit DMA Controller block (TMAC) is stored in channel specific FIFOs

residing in the partial packet buffer. When the amount of data in a FIFO reaches a programmable

threshold, the HDLC controller is enabled to initiate transmission. The HDLC controller performs

flag generation, bit stuffing and, optionally, frame check sequence (FCS) insertion. The FCS is

software selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding FCS, is

two bytes. A single byte payload is illegal. The HDLC controller delivers data to the Transmit

Channel Assigner block (TCAS) on demand. A packet in progress is aborted if an under-run

occurs. The THDL is programmable to operate in transparent mode where packet data retrieved

from the PCI host is transmitted verbatim.

9.7.1

Transmit HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 128 independent

channels. The state vector and provisioning information for each channel is stored in a RAM.

Whenever the TCAS requests data, the appropriate state vector is read from the RAM, processed

and finally written back to the RAM. The HDLC state-machine can be configured to perform flag

insertion, bit stuffing and CRC generation. The HDLC processor requests data from the partial

packet processor whenever a request for channel data arrives. However, the HDLC processor

does not start transmitting a packet until the entire packet is stored in the channel FIFO or until the

FIFO free space is less than the software programmable limit. If a channel FIFO under-runs, the

HDLC processor aborts the packet.

The configuration of the HDLC processor is accessed using indirect channel read and write

operations. When an indirect operation is performed, the information is accessed from RAM

during a null clock cycle inserted by the TCAS block. Writing new provisioning data to a channel

resets the channel's entire state vector.

9.7.2

Transmit Partial Packet Buffer Processor

The partial packet buffer processor controls the 8 Kbyte partial packet RAM which is divided into

16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular

channel FIFO buffers. Thus, non-contiguous sections of RAM can be allocated in the partial

packet buffer RAM to create a channel FIFOFigure 15 shows an example of three blocks (blocks

1, 3, and 200) linked together to form a 48 byte channel FIFO. The three pointer values would be

written sequentially using indirect block write accesses. When a channel is provisioned with this

FIFO, the state machine can be initialised to point to any one of the three blocks.

PM7366-PI Datasheet(PDF) 80 Page - PMC-Sierra, Inc

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