PM7366-PI datasheet(221/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

208

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

OF[15]

Bit 14

OF[14]

Bit 13

OF[13]

Bit 12

OF[12]

Bit 11

OF[11]

Bit 10

OF[10]

Bit 9

OF[9]

Bit 8

OF[8]

Bit 7

OF[7]

Bit 6

OF[6]

Bit 5

OF[5]

Bit 4

OF[4]

Bit 3

OF[3]

Bit 2

OF[2]

Bit 1

OF[1]

Bit 0

OF[0]

This register reports the number of receive FIFO overflow events in the previous accumulation

interval.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

OF[15:0]:

The OF[15:0] bits reports the number of receive FIFO overflow events that have been

detected since the last time this register was polled. This register is polled by writing to the

FREEDM-8 Master Clock / BERT Activity Monitor and Accumulation Trigger register. The

PM7366-PI Datasheet(PDF) 221 Page - PMC-Sierra, Inc

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