PM7366-PI datasheet(258/286 Pages) PMC

258 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

245

Test-Logic-Reset

The test logic reset state is used to disable the TAP logic when the device is in normal mode

operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered

synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK

clock cycles. While in this state, the instruction register is set to the IDCODE instruction.

Run-Test-Idle

The run test/idle state is used to execute tests.

Capture-DR

The capture data register state is used to load parallel data into the test data registers selected by

the current instruction. If the selected register does not allow parallel loads or no loading is

required by the current instruction, the test register maintains its value. Loading occurs on the

rising edge of TCK.

Shift-DR

The shift data register state is used to shift the selected test data registers by one stage. Shifting

is from MSB to LSB and occurs on the rising edge of TCK.

Update-DR

The update data register state is used to load a test register's parallel output latch. In general, the

output latches are used to control the device. For example, for the EXTEST instruction, the

boundary scan test register's parallel output latches are used to control the device's outputs. The

parallel output latches are updated on the falling edge of TCK.

Capture-IR

The capture instruction register state is used to load the instruction register with a fixed

instruction. The load occurs on the rising edge of TCK.

Shift-IR

The shift instruction register state is used to shift both the instruction register and the selected test

data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.

PM7366-PI Datasheet(PDF) 258 Page - PMC-Sierra, Inc