PM7366-PI datasheet(271/286 Pages) PMC

271 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

258

target stops driving the AD[31:0] bus and the initiator stops driving the C/BEB[3:0] bus. This shall

be the turnaround cycle for these signals.

Figure 35 – PCI Fast Back to Back

PCICLK

FRAMEB

AD[31:0]

C/BEB[3:0]

IRDYB

TRDYB

DEVSELB

Address

Data

Byte En

Byte Enable

Bus Cmd

Address

Data

Bus Cmd

14.4 BERT Interface

The timing relationship between the receive link clock and data (RCLK[n] / RD[n]) and the receive

BERT port signals (RBCLK / RBD) is shown in Figure 36. The selected RCLK[n] is placed on

RBCLK after an asynchronous delay. The selected receive link data (RD[n]) is sampled on the

rising edge of the associated RCLK[n] and transferred to RBD on the falling edge of RBCLK.

Figure 36 – Receive BERT Port Timing

RCLK[n]

RD[n]

B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X

RBCLK

RBD

B1 B2 B3

B6 B7 B8 B1

The timing relationship between the transmit link clock and data (TCLK[n] / TD[n]) and the

transmit BERT port signals (TBCLK / TBD) is shown in Figure 37. TCLK[n] is shown to have an

arbitrary gapping. When TCLK[n] is quiescent, TBD is ignored (X in Figure 37). The selected

TCLK[n] is buffered and placed on TBCLK. The transmit BERT data (TBD) is sampled on the

rising edge of the TBCLK and transferred to the selected TD[n] on the falling edge of TCLK[n].

PM7366-PI Datasheet(PDF) 271 Page - PMC-Sierra, Inc

PM7366-PI Datasheet(HTML) 271 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL