PM7366-PI datasheet(114/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

101

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

BUSY

Bit 14

R/W

RWB

Bit 13

Unused

Bit 12

R/W

Reserved[1]

Bit 11

R/W

Reserved[0]

Bit 10

R/W

LINK[2]

Bit 9

R/W

LINK[1]

Bit 8

R/W

LINK[0]

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

TSLOT[4]

Bit 3

R/W

TSLOT[3]

Bit 2

R/W

TSLOT[2]

Bit 1

R/W

TSLOT[1]

Bit 0

R/W

TSLOT[0]

This register provides the receive link and time-slot number used to access the channel provision

RAM. Writing to this register triggers an indirect register access.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

TSLOT[4:0]:

The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or

interrogated in the indirect access. For a channelised T1 link, time-slots 1 to 24 are valid. For

a channelised E1 link, time-slots 1 to 31 are valid. For unchannelised links, only time-slot 0 is

valid.

PM7366-PI Datasheet(PDF) 114 Page - PMC-Sierra, Inc

PM7366-PI Datasheet(HTML) 114 Page - PMC-Sierra, Inc

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