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PM7366-PI Datasheet(PDF) 119 Page - PMC-Sierra, Inc |
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PM7366-PI Datasheet(HTML) 119 Page - PMC-Sierra, Inc |
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119 / 286 page ![]() RELEASED PM7366 FREEDM-8 DATA SHEET PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 106 link is set high, the counter is cleared at every fourth rising edge of the corresponding RCLK[n]. When the counter exceeds the threshold given by FTHRES[6:0], a framing bit/byte has been detected. FTHRES[6:0] should be set as a function of the SYSCLK period and the expected gapping width of RCLK[n] during data bits and during framing bits/bytes. Legal range of FTHRESH[6:0] is 'b0000001 to 'b1111110. Note: For operation with T1 links and SYSCLK = 33 MHz, FTHRESH[6:0] should be set to ‘b0011111’. The default value of this register is inconsistent with that of the TCAS Framing Bit Threshold register 0x408. |
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