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RM5261 Datasheet(PDF) 33 Page - PMC-Sierra, Inc |
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RM5261 Datasheet(HTML) 33 Page - PMC-Sierra, Inc |
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33 / 40 page ![]() Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 33 Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 9 AC Electrical Characteristics 9.1 Capacitive Load Deration 9.2 Clock Parameters Parameter Symbol Min Max Units Load Derate CLD 2 ns/25pF IO Power Derate 21 mW/25pF/MHz IO Power Derate @ 20pF load 4.0 5.5 mW/MHz Parameter Symbol Test Conditions CPU Speed Units 200 MHz 250 MHz 266 MHz Min Max Min Max Min Max SysClock High tSCH Transition ≤ 5ns 3 3 3 ns SysClock Low tSCL Transition ≤ 5ns 3 3 3 ns SysClock Frequency1 25 100 25 125 33.3 106 MHz SysClock Period tSCP 40 40 30 ns Clock Jitter for SysClock tJI ±200 ±150 ±150 ps SysClock Rise Time tCR 222 ns SysClock Fall Time tCF 222 ns ModeClock Period tModeCKP 256 256 256 tSCP JTAG Clock Period tJTAGCKP 444 tSCP Note 1. Operation of the RM5261 is only guaranteed with the Phase Lock Loop Enabled. |
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