RM5261 datasheet(12/40 Pages) PMC

12 / 40 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002241, Issue 1

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

Released

multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-

operand integer multiply/divide operations, and the program counter (PC).

3.4

Pipeline

For integer operations, loads, stores, and other non-floating-point operations, the RM5261

implements a 5-stage integer pipeline. In addition to the integer pipeline, the RM5261 implements

an extended 7-stage pipeline for floating-point operations.

The RM5261 multiplies the input SysClock by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the

pipeline clock.

Figure 3 shows the RM5261 integer pipeline. As illustrated in the figure, up to five integer

instructions can be executing simultaneously.

Figure 3 Pipeline

3.5

The RM5261 has thirty-two general purpose registers with register location 0 (r0) hard-wired to a

zero value. These registers are used for scalar integer operations and address calculation. The

latency in the pipeline.

3.6

ALU

The RM5261 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder

performs address calculations in addition to arithmetic operations. The logic unit performs all

logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each

of these units is optimized to perform all operations in a single processor cycle.

one cycle

1I-1R:

2I:

2A-2D:

2R:

1A-2A:

1A:

1D:

2A:

2W:

Instruction cache access

Instruction virtual to physical address translation

Issue or slip decision, Branch decision

Integer add, logical, shift

Data virtual address calculation

Data virtual to physical address translation

Store Align

Data cache access and load align

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