RM5261 datasheet(11/40 Pages) PMC

11 / 40 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002241, Issue 1

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

Released

Hardware Overview

The RM5261 offers a high-level of integration targeted at high-performance embedded

applications. The key elements of the RM5261 are briefly described below.

3.1

Superscalar Dispatch

The RM5261 has an asymmetric superscalar dispatch unit which allows it to issue an integer

instruction and a floating-point computation instruction simultaneously. Integer instructions

include alu, branch, load/store, and floating-point load/store, while floating-point computation

instructions include floating-point add, subtract, combined multiply-add, converts, etc. In

combination with its high-throughput fully pipelined floating-point execution unit, the superscalar

capability of the RM5261 provides unparalleled price/performance in computationally intensive

embedded applications.

3.2

CPU Registers

The RM5261 CPU has a simple user-visible state consisting of 32 general purpose registers, two

special purpose registers for integer multiplication and division, a program counter, and no

condition code bits. Figure 2 shows the user visible state.

Figure 2 CPU Registers

3.3

Integer Unit

Like the RM5260, the RM5261 implements the MIPS IV Instruction Set Architecture, and is

therefore fully upward compatible with applications that run on processors implementing the

earlier generation MIPS I-III instruction sets. Additionally, the RM5261 includes three

implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in

the embedded market place. Described in detail in a later section, these instructions are integer

multiply-accumulate and 3-operand integer multiply.

The RM5261 integer unit includes thirty-two general purpose 64-bit registers, a load/store

architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous

General Purpose Registers

Multiply/Divide Registers

•

Program Counter

•

r29

r30

r31

RM5261 Datasheet(PDF) 11 Page - PMC-Sierra, Inc