RM5261 datasheet(18/40 Pages) PMC

18 / 40 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002241, Issue 1

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

Released

reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time

systems by allowing deterministic access to critical software.

The JTLB also contains information that controls the cache coherency protocol for each page.

Specifically, each page has attribute bits to determine whether the coherency algorithm is one of

the following:

•

uncached

•

non-coherent write-back

•

non-coherent write-through with write-allocate

•

non-coherent write-through without write-allocate

•

sharable

•

exclusive

•

update.

The non-coherent protocols are used for both code and data on the RM5261, with data using write-

back or write-through depending on the application.

The coherency attributes generate coherent transaction types on the system interface. However, in

the RM5261 cache coherency is not supported. Hence the coherency attributes should never be

used.

3.15 Instruction TLB

The RM5261 implements a 2-entry instruction TLB (ITLB) to minimize contention for the JTLB,

eliminate the timing critical path of translating through a large associative array, and save power.

Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction

address translation to occur in parallel with data address translation. When a miss occurs on an

instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the

JTLB. The operation of the ITLB is completely transparent to the user.

3.16 Data TLB

The RM5261 implements a 4-entry data TLB (DTLB) for the same reasons cited above for the

ITLB. Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data

address translation to occur in parallel with instruction address translation. When a miss occurs on

a data address translation by the DTLB, the DTLB is filled from the JTLB. The DTLB refill is

pseudo-LRU: the least recently used entry of the least recently used pair of entries is filled. The

operation of the DTLB is completely transparent to the user.

3.17 Cache Memory

The RM5261 incorporates on-chip instruction and data caches that can be accessed in a single

processor cycle. Each cache has its own 64-bit data path and both caches can be accessed

simultaneously. The cache subsystem provides the integer and floating-point units with an

aggregate bandwidth of 3.2 GB per second at an internal clock frequency of 200 MHz.

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